URAT=IDR_WR_PROCESSING
Interrupt Status Register
| DATRDY | Data Ready (cleared by setting bit START or bit SWRST in AES_CR or by reading AES_ODATARx) |
| URAD | Unspecified Register Access Detection Status (cleared by writing SWRST in AES_CR) |
| URAT | Unspecified Register Access (cleared by writing SWRST in AES_CR) 0 (IDR_WR_PROCESSING): Input Data register written during the data processing when SMOD = 0x2 mode. 1 (ODR_RD_PROCESSING): Output Data register read during the data processing. 2 (MR_WR_PROCESSING): Mode register written during the data processing. 3 (ODR_RD_SUBKGEN): Output Data register read during the sub-keys generation. 4 (MR_WR_SUBKGEN): Mode register written during the sub-keys generation. 5 (WOR_RD_ACCESS): Write-only register read access. |
| TAGRDY | GCM Tag Ready |